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1 of 22 rev: 042208 d escription the ds18b20 digital thermometer provides 9 - bit to 12 - bit celsius temperature measurements and has an alarm function with nonvolatile user - programmable upper and lower trigger points. the ds18b20 communicates over a 1- wire bus that by definition requires only one data line (and ground) for communication with a central microprocessor. it has an operating temperature range of - 55c to +125c and is accurate to 0.5 c over the range of - 10c to +85c . in addition, th e ds18b20 can derive power directly from the data line (?parasite power?), eliminating the need for an external power supply. each ds18b20 has a unique 64 - bit serial code, which allows multiple ds18b20s to function on the same 1 - w ire bus . t hus, it i s simple to use one microprocessor to control many ds18b20s distributed over a large area. applications that can benefit from this feature include hvac environmental controls, temperature monitoring systems inside buildings, equipment , or machinery, and pr ocess monitoring and control systems. features ? unique 1 - wire ? interface requires only one port pin for communication ? each device has a unique 64 - bit serial code stored in an on -b oard rom ? multidrop capability simplifies distributed temperature - sensing applications ? requires no external components ? can be powered from data line ; power supply range is 3.0v to 5.5v ? measures temperatures from - 55c to +125c (- 67f to +257f) ? 0.5 c accuracy from - 10c to +85c ? thermometer resolution is user selectable from 9 to 12 bits ? conver ts temperature to 12 - bit digital word in 750ms (max ) ? user - definable nonvolatile (nv) alarm settings ? alarm search command identifies and addresses devices whose temperature is outside programmed limits (temperature alarm condition) ? available in 8 - pin so (150 mil s ), 8- pin sop, and 3 - pin to - 92 packages ? software compatible with the ds1822 ? applications include thermostatic controls, industrial systems, consumer products, thermometers, or any thermally sensitive system pin configurations ds18b20 programmable resolution 1 - wire digital thermometer to - 92 (ds18b20) 1 (bottom view) 2 3 maxim 18b20 1 gnd dq v dd 2 3 so (150 mils) (ds18b20z) n . c . n . c . n . c . n . c . gnd dq v dd n . c . 6 8 7 5 3 1 2 4 maxim 18b20 n . c . v dd n . c . n . c . n . c . gnd n . c . dq 6 8 7 5 3 1 2 4 18b20 sop (ds18b20u) 1 - wire is a registered trademark of maxim integrated products, inc.
ds18b20 2 of 22 order ing information part temp range pin - package top mark ds18b20 - 55 c to +125 c 3 to - 92 18b20 ds18b20+ - 55 c to +125 c 3 to - 92 18b20 ds18b20/t&r - 55 c to +125c 3 to - 92 ( 2000 piece ) 18b20 ds18b20+t&r - 55 c to +125c 3 to - 92 ( 2000 piece ) 18b20 ds18b20 - sl/t&r - 55 c to +125 c 3 to - 92 (2000 piece)* 18b20 ds18b20 - sl+t&r - 55 c to +125 c 3 to - 92 (2000 piece)* 18b 20 ds18b20u - 55 c to +125 c 8 sop 18b20 ds18b20u+ - 55 c to +125 c 8 sop 18b20 ds18b20u/t&r - 55 c to +125 c 8 sop ( 3000 piece ) 18b20 ds18b20u+t&r - 55 c to +125 c 8 sop ( 3000 piece ) 18b20 ds18b20z - 55 c to +125 c 8 so ds18b20 ds18b20z+ - 55 c to +125 c 8 so ds18b20 ds18b20z/t&r - 55 c to +125 c 8 so ( 2500 piece ) ds18b20 ds18b20z+t&r - 55 c to +125c 8 so ( 2500 piece ) ds18b20 + denotes a lead - free package. a ?+? will appear on the top mark of lead - free packages. t&r = tape and reel. * to - 92 packages in ta pe and reel can be ordered with straight or formed leads. choose ? sl ? for straight lead s . bulk to - 92 orders are straight leads only. pin description pin name function so sop to - 92 1, 2, 6, 7, 8 2, 3, 5, 6, 7 ? n.c . no connection 3 8 3 v dd optional v dd . v dd must be grounded for operation in parasite power mode. 4 1 2 dq data input/output . open - drain 1- wire interface pin. also provides power to the device when used in parasite power mode (see the powering the d s18b20 section.) 5 4 1 gnd ground overview figure 1 shows a block diagram of the ds18b20, and pin descriptions are given in the pin descripti on table . the 64 - bit rom stores the device?s unique serial code. the scratchpad memory contains the 2 - byte temperature register that stores the digital output from the temperature sensor. in addition, the scratchpad provides access to the 1 - byte upp er and lower alarm trigger registers (t h and t l ) and the 1 - byte configuration register. the configuration register allows the user to set the resolution of the temperature - to - digital conversion to 9, 10, 11, or 12 bits. the t h , t l , and configuration regis ters are nonvolatile (eeprom), so they will retain data when the device is powered down. the ds18b20 uses maxim?s exclusive 1- wire bus protocol that implements bus communication using one control signal. the control line requires a weak pullup res istor since all devices are linked to the bus via a 3- state or open - drain port (the dq pin in the case of the ds18b20). in this bus system, the microprocessor (the master device) identifies and addresses devices on the bus using each device?s unique 64- bi t code. because each device has a unique code, the number of devices that can be addressed on one
ds18b20 3 of 22 bus is virtually unlimited. the 1- wire bus protocol, including detailed explanations of the commands and ?time slots,? is covered in the 1- wire bus system se ction . another feature of the ds18b20 is the ability to operate without an external power supply. power is instead supplied through the 1- wire pullup resistor via the dq pin when the bus is high. the high bus signal also charges an intern al capacitor (c pp ), which then supplies power to the device when the bus is low. this method of deriving power from the 1- wire bus is referred to as ?parasite power.? as an alternative, the ds18b20 may also be powered by an external supply on v dd . figure 1 . ds18b20 block diagram operation ? measuring temperature the core functionality of the ds18b20 is its direct - to - digital temperature sensor. the resolution of the temperature sensor is user - configurab le to 9, 10, 11, or 12 bits, corresponding to increments of 0.5 c, 0.25 c, 0.125 c, and 0.0625 c, respectively. the default resolution at power - up is 12 - bit. the ds18b20 powers up in a low - power idle state . t o initiate a temperature measurement and a - to - d conversion, the master must issue a convert t [44h] command. following the conversion, the resulting thermal data is stored in the 2 - byte temperature register in the scratchpad memory and the ds18b20 returns to its idle state. if the ds18b20 is powered by an external supply, the master can issue ?read time slots? (see the 1- wire bus system section) after the convert t command and the ds18b20 will respond by transmitting 0 while the temperature conversion is in progress and 1 when the conversion is don e. if the ds18b20 is powered with parasite power, this notification technique cannot be used since the bus must be pulled high by a strong pullup during the entire temperature conversion. the bus requirements for parasite power are explained in detail in t he powering t he ds18b20 section . the ds18b20 output temperature data is calibrated in degrees celsius ; for fahrenheit applications, a lookup table or conversion routine must be used. the temperature data is stored as a 16 - bit s ign - extended two?s complement number in the temperature register (see figure 2 ). the sign bits (s) indicate if the temperature is positive or negative: for positive numbers s = 0 and for negative numbers s = 1. if the ds18 b20 is configured for 12 - bit resolution, all bits in the temperature register will contain valid data. for 11 - bit resolution, bit 0 is undefined. for 10 - bit resolution, bits 1 and 0 are undefined, and for 9 - bit resolution bits 2, 1 , and 0 are undefined. table 1 gives examples of digital output data and the corresponding temperature reading for 12 - bit resolution conversions. v pu 4.7k power - supply sense 64 - bit rom and 1 - w ire port dq v dd internal v dd c pp parasite power circuit memory control logic scratchpad 8 - bit crc generator temperature sensor alarm high trigger (t h ) register (eeprom) alarm low trigger (t l ) register (eeprom) configuration register (eeprom) gnd ds18b20
ds18b20 4 of 22 figure 2 . temperature register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ls byte 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ms byte s s s s s 2 6 2 5 2 4 s = sign table 1 . temperature/data relationship temperature ( c) digital out put (binary) digital output (hex) +125 0000 0111 1101 0000 07d0h +85 * 0000 0101 0101 0000 0550h +25.0625 0000 0001 1001 0001 0191h +10.125 0000 0000 1010 0010 00a2h +0.5 0000 0000 0000 1000 0008h 0 0000 0000 0000 0000 0000h - 0.5 1111 1 111 1111 1000 fff8h - 10.125 1111 1111 0101 1110 ff5eh - 25.0625 1111 1110 0110 1111 fe6fh - 55 1111 1100 1001 0000 fc90h * the power - on reset value of the temperature register is +85c . operation ? alarm signaling after the ds18b20 performs a tempe rature conversion, the temperature value is compared to the user - defined two?s complement alarm trigger values stored in the 1 - byte t h and t l registers (see figure 3). the sign bit (s) indicates if the value is positive or negative: for positive numbers s = 0 and for negative numbers s = 1 . the t h and t l registers are nonvolatile (eeprom) so they will retain data when the device is powered down. t h and t l can be accessed through bytes 2 and 3 of the scratchpad as explained in the memory section . figure 3 . t h and t l register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 only bits 11 through 4 of the temperature register are used in th e t h and t l comparison since t h and t l are 8 - bit registers. if the measured temperature is lower than or equal to t l or higher than or equal to t h , an alarm condition exists and an alarm flag is set inside the ds18b20. this flag is updated after every temp erature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the next temperature conversion.
ds18b20 5 of 22 the master device can check the alarm flag status of all ds18b20s on the bus by issuing an alarm search [ech] command. any ds18b20s with a set alarm flag will respond to the command, so the master can determine exactly which ds18b20s have experienced an alarm condition. if an alarm condition exists and the t h or t l settings have changed, another temperature conversion should be done to validate the alarm condition. powering the ds18b20 the ds18b20 can be powered by an external supply on the v dd pin, or it can operate in ?parasite power? mode, which allows the ds18b20 to function without a local external supply. parasite pow er is very useful for applications that require remote temperature sensing or that are very space constrained. figure 1 shows the ds18b20?s parasite - power control circuitry, which ?steals? power from the 1 - wire bus via th e dq pin when the bus is high. the stolen charge powers the ds18b20 while the bus is high, and some of the charge is stored on the parasite power capacitor (c pp ) to provide power when the bus is low. when the ds18b20 is used in parasite power mode, the v dd pin must be connected to ground. in parasite power mode, the 1 - wire bus and c pp can provide sufficient current to the ds18b20 for most operations as long as the specified timing and voltage requirements are met ( see the dc electrical character istics and ac electrical characteristics ). however, when the ds18b20 is performing temperature conversions or copying data from the scratchpad memory to eeprom, the operating current can be as high as 1.5ma. this current can cause an unacceptable voltage drop across the weak 1 - wire pullup resistor and is more current than can be supplied by c pp . to assure that the ds18b20 has sufficient supply current, it is necessary to provide a strong pullup on the 1 - wire bus whenever temp erature conversions are taking place or data is being copied from the scratchpad to eeprom. this can be accomplished by using a mosfet to pull the bus directly to the rail as shown in figure 4 . the 1 - wire bus must be switc hed to the strong pullup within 10 s (max) after a convert t [44h] or copy scratchpad [48h] command is issued, and the bus must be held high by the pullup for the duration of the conversion (t conv ) or data transfer (t wr = 10ms). no other activity can take place on the 1 - wire bus while the pullup is enabled. the ds18b20 can also be powered by the conventional method of connecting an external power supply to the v dd pin, as shown in figure 5 . the advantage of this method is that the mosfet pullup is not req uired, and the 1 - wire bus is free to carry other traffic during the temperature conversion time. the use of parasite power is not recommended for temperatures above +100 c since the ds18b20 may not be able to sustain communications due to the higher leakage currents that can exist at these temperatures. for applications in which such temperatures are likely, it is strongly recommended that the ds18b20 be powered by an ext ernal power supply. in some situations the bus master may not know whether the ds18b20s on the bus are parasite powered or powered by external supplies. the master needs this information to determine if the strong bus pullup should be used during temperat ure conversions. to get this information, the master can issue a skip rom [cch] command followed by a read power supply [ b4h ] command followed by a ?read time slot?. during the read time slot, parasite powered ds18b20s will pull the bus low, and externally powered ds18b20s will let the bus remain high. if the bus is pulled low, the master knows that it must supply the strong pullup on the 1 - wire bus during temperature conversions.
ds18b20 6 of 22 figure 4 . supplying t he parasite - powered d s18b20 during temperature conversions figure 5 . powering t he ds18b20 with an external supply 64- bit lasered rom code each ds18b20 contains a unique 64 ? bit code (see figure 6 ) stored in rom. the least significant 8 bits of the rom code contain the ds18b20?s 1 - wire family code: 28h. the next 48 bits contain a unique serial number. the most significant 8 bits contain a cyclic redundancy check (crc ) byte that is calculated from the first 56 bits of the rom code. a detailed explanation of the crc bits is provided in the crc generation section. the 64 - bit rom code and associated rom function control logic allow the ds18b20 to operate as a 1 - wire devic e using the protocol detailed in the 1- wire bus system section . figure 6 . 64 - bit lasered rom code 8 - bit crc 48 - bit serial number 8 - bit family code (28h) msb msb lsb lsb lsb msb v pu v pu 4.7k 1 - wire bus p ds18b20 gnd v dd dq to other 1 - wire devices v dd (external supply) ds18b20 gnd v dd dq v pu 4.7k t o other 1 - wire devices 1 - wire b us p
ds18b20 7 of 22 memory the ds18b20?s memory is organized as shown in figure 7 . the memory consists of an sram scratchpad with nonvolatile eeprom storage for the high and low alarm trigger registers (t h and t l ) and configuration register. note that if the ds18b20 alarm function i s not used, the t h and t l registers can serve as general - purpose memory. all memory commands are described in detail in the ds18b20 function commands section. byte 0 and byte 1 of the scratchpad contain the lsb and the msb of the temperature register, resp ectively. these bytes are read - only. bytes 2 and 3 provide access to t h and t l registers. byte 4 contains the configuration register data, which is explained in detail in the configuration register section . bytes 5, 6, and 7 are reserved for internal use by the device and cannot be overwritten. byte 8 of the scratchpad is read - only and contains the crc code for bytes 0 through 7 of the scratchpad. the ds18b20 generates this crc using the method described in the c rc generation section. data is written to bytes 2, 3, and 4 of the scratchpad using the write scratchpad [4eh] command; the data must be transmitted to the ds18b20 starting with the least significant bit of byte 2. to verify data integrity, the scratchpad can be read (using the read scratchpad [beh] command) after the data is written. when reading the scratchpad, data is transferred over the 1- wire bus starting with the least significant bit of byte 0. to transfer the t h , t l and configuration data from the scratchpad to eeprom, the master must issue the copy scratchpad [48h] command. data in the eeprom registers is retained when the device is powered down; at power - up the eeprom data is reloaded into the corresponding scratchpad locations. data can a lso be reloaded from eeprom to the scratchpad at any time using the recall e 2 [b8h] command. the master can issue read time slots following the recall e 2 command and the ds18b20 will indicate the status of the recall by transmitting 0 while the recall is i n progress and 1 when the recall is done. figure 7 . ds18b20 memory map scratchpad (power - u p state ) byte 0 temperature lsb (50h) byte 1 temperature msb (05h) eeprom byte 2 t h register or user byte 1* t h register or user byte 1 byte 3 t l register or user byte 2* t l register or user byte 2 byte 4 configuration register* configuration register byte 5 reserved (ffh) byte 6 reserved byte 7 reserved (10h) byte 8 crc* * power - up state depends on value(s) stored in eeprom . (85c)
ds18b20 8 of 22 configuration regist er byte 4 of the scratchpad memory contains the configuration register, which is organized as illustrated in figure 8. the user can set the conversion resolution of the d s18b20 using the r0 and r1 bits in this register as shown in table 2. the power - up default of these bits is r0 = 1 and r1 = 1 (12 - bit resolution). note that there is a direct tradeoff between resolution and conversion time . bit 7 and bits 0 to 4 in the configuration register are reserved for internal use by the device and cannot be overwritten. figure 8 . configuration register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 r1 r0 1 1 1 1 1 table 2 . thermometer resolution configuration r1 r0 resolution (bits) max conversion time 0 0 9 93.75 ms (t conv /8) 0 1 10 187.5 ms (t conv /4) 1 0 11 375 ms (t conv /2) 1 1 12 750 ms (t conv ) crc generation crc bytes are provided as part of the ds18b20?s 64 - bit rom code and in the 9 th byte of the scratchpad memory. the rom code crc is calculated from the first 56 bits of the rom code and is contained in the most significant byte of the rom. the scr atchpad crc is calculated from the data stored in the scratchpad, and therefore it changes when the data in the scratchpad changes. the crcs provide the bus master with a method of data validation when data is read from the ds18b20. to verify that data h as been read correctly, the bus master must re - calculate the crc from the received data and then compare this value to either the rom code crc (for rom reads) or to the scratchpad crc (for scratchpad reads). if the calculated crc matches the read crc, the data has been received error free. the comparison of crc values and the decision to continue with an operation are determined entirely by the bus master. there is no circuitry inside the ds18b20 that prevents a command sequence from proceeding if the ds18b 20 crc (rom or scratchpad) does not match the value generated by the bus master. the equivalent polynomial function of the crc (rom or scratchpad) is: crc = x 8 + x 5 + x 4 + 1 the bus master can re - calculate the crc and compare it to the crc values from t he ds18b20 using the polynomial generator shown in figure 9 . this circuit consists of a shift register and xor gates, and the shift register bits are initialized to 0. starting with the least significant bit of the rom cod e or the least significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. after shifting in the 56 th bit from the rom or the most significant bit of byte 7 from the scratchpad, the polynomial generator will conta in the re - calculated crc. next, the 8 - bit rom code or scratchpad crc from the ds18b20 must be shifted into the circuit. at this point, if the re - calculated crc was correct, the shift register will contain all 0s. additional information about the max im 1- wire cyclic redundancy check
ds18b20 9 of 22 is available in application note 27: understanding and using cyclic redundancy checks with maxim i button products . figure 9 . crc generator 1 - wire bus system the 1 - wire bus system uses a single bus master to control one or more slave devices. the ds18b20 is always a slave. when there is only one slave on the bus, the system is referred to as a ?single - drop? system; the system is ?multidro p? if there are multiple slaves on the bus. all data and commands are transmitted least significant bit first over the 1 - wire bus. the following discussion of the 1 - wire bus system is broken down into three topics: hardware configuration, transaction sequ ence, and 1 - wire signaling (signal types and timing). hardware configuration the 1- wire bus has by definition only a single data line. each device (master or slave) interfaces to the data line via an open - drain or 3 - state port. this allows each device to ?release? the data line when the device is not transmitting data so the bus is available for use by another device. the 1- wire port of the ds18b20 (the dq pin) is open drain with an internal circuit equivalent to that shown in figu re 10. the 1 - wire bus requires an external pullup resistor of approximately 5k ? ; thus, the idle state for the 1- wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction i s to resume. infinite recovery time can occur between bits so long as the 1 - wire bus is in the inactive (high) state during the recovery period. if the bus is held low for more than 480 s, all components on the bus will be reset. figure 10. hardware configuration (msb) (lsb) xor xor xor input v pu 4.7k 5a typ r x t x ds18b20 1 - w ire port 10 0 ? mosfet t x rx r x = receive t x = tra nsmit 1 - wire bus dq p in
ds18b20 10 of 22 transaction sequence the transaction sequence for accessing the ds18b20 is as follows: step 1. initialization step 2. rom command (followed by any required data exchange) step 3. ds18b20 fun ction command (followed by any required data exchange) it is very important to follow this sequence every time the ds18b20 is accessed, as the ds18b20 will not respond if any steps in the sequence are missing or out of order. exceptions to this rule are th e search rom [f0h] and alarm search [ech] commands. after issuing either of these rom commands, the master must return to step 1 in the sequence. initialization all transactions on the 1 - wire bus begin with an initialization sequence. the initializatio n sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that slave devices (such as the ds18b20) are on the bus and are ready to operate. timi ng for the reset and presence pulses is detailed in the 1- wire signaling section. rom commands after the bus master has detected a presence pulse, it can issue a rom command. these commands operate on the unique 64 - bit rom codes of each slave device and allow the master to single out a specific device if many are present on the 1 - wire bus. these commands also allow the master to determine how many and what types of devices are present on the bus or if any device has experienced an alarm condition. there are five rom commands, and each command is 8 bits long. the master device must issue an appropriate rom command before issuing a ds18b20 function command. a flowchart for operation of the rom commands is shown in figure 11. search rom [f0h] when a system is initially powered up, the master must identify the rom codes of all slave devices on the bus, which allows the master to determine the number of slaves and their device types. the master learns the rom codes through a process of elimination that requires the master to perform a search rom cycle (i.e., search rom command followed by data exchange) as many times as necessary to identify all of the slave devices. if there is only one slave on the bus, the simpler read rom command (see below) can be used in place of the search rom process. for a detailed explanation of the search rom procedure, refer to the i button ? book of standards at www.maxim - ic.com/ ibuttonbook . after every search rom cycle, the bus master must return to step 1 (initialization) in the transaction sequence. read rom [33h] this command can only be used when there is one slave on the bus. it allows the bus master to read the slave?s 64 - bit rom code without using the search rom procedure. if this command is used when there is more than one slave present on the bus, a data collision will occur when all the slaves attempt to respond at the same time. match rom [55h] the match rom command followed by a 64 - bit rom code sequence allows the bus master to address a specific slave device on a multidrop or single - drop bus. only the slave that exactly matches the 64 - bit rom code sequence will respond to the function command issued by the master; all other slaves on the bus will wait for a reset pulse. i button is a registered trademark of maxim integrated products, inc.
ds18b20 11 of 22 skip rom [cch] the master can use this command to address all devices on the bus simultaneously without sending out any rom code information. for example, the master can make a ll ds18b20s on the bus perform simultaneous temperature conversions by issuing a skip rom command followed by a convert t [44h] command. note that the read scratchpad [beh] command can follow the skip rom command only if there is a single slave device on the bus. in this case , time is saved by allowing the master to read from the slave without sending the device?s 64 - bit rom code. a skip rom command followed by a read scratchpad command will cause a data collision on the bus if there is more than one slave since multiple devices will attempt to transmit data simultaneously. alarm search [ech] the operation of this command is identical to the operation of the search rom command except that only slaves with a set alarm flag will respond. this command allow s the master device to determine if any ds18b20s experienced an alarm condition during the most recent temperature conversion. after every alarm search cycle (i.e., alarm search command followed by data exchange), the bus master must return to step 1 (init ialization) in the transaction sequence. see the operation ? alarm signaling section for an explanation of alarm flag operation. ds18b20 function commands after the bus master has used a rom command to address the ds18b20 with which it wishes to communicate, the master can issue one of the ds18b20 function commands. these commands allow the master to write to and read from the ds18b20?s scratchpad memory, initiate temperature conversions and determine the power supply mode. the ds18b20 function c ommands, which are described below, are summarized in table 3 and illustrated by the flowchart in figure 12. convert t [44h] this command initiates a single temperature conversion. followi ng the conversion, the resulting thermal data is stored in the 2 - byte temperature register in the scratchpad memory and the ds18b20 returns to its low - power idle state. if the device is being used in parasite power mode, within 10 s (max) after this comman d is issued the master must enable a strong pullup on the 1- wire bus for the duration of the conversion (t conv ) as described in the powering t he ds18b20 section. if the ds18b20 is powered by an external supply, the master can issue read time slots after the convert t command and the ds18b20 will respond by transmitting a 0 while the temperature conversion is in progress and a 1 when the conversion is done. in parasite power mode this notification technique cannot be used since the bus is pulled high by t he strong pullup during the conversion. write scratchpad [4eh] this command allows the master to write 3 bytes of data to the ds18b20?s scratchpad. the first data byte is written into the t h register (byte 2 of the scratchpad), the second byte is written i nto the t l register (byte 3), and the third byte is written into the configuration register (byte 4). data must be transmitted least significant bit first. all three bytes must be written before the master issues a reset, or the data may be corrupted. read scratchpad [beh] this command allows the master to read the contents of the scratchpad. the data transfer starts with the least significant bit of byte 0 and continues through the scratchpad until the 9 th byte (byte 8 ? crc) is read. the master may issu e a reset to terminate reading at any time if only part of the scratchpad data is needed.
ds18b20 12 of 22 copy scratchpad [48h] this command copies the contents of the scratchpad t h , t l and configuration registers (bytes 2, 3 and 4) to eeprom. if the device is being used in parasite power mode, within 10 s (max) after this command is issued the master must enable a strong pullup on the 1- wire bus for at least 10ms as described in the powering t he ds18b20 section. recall e 2 [b8h] this command recalls the alarm trigger valu es (t h and t l ) and configuration data from eeprom and places the data in bytes 2, 3, and 4, respectively, in the scratchpad memory. the master device can issue read time slots following the recall e 2 command and the ds18b20 will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. the recall operation happens automatically at power - up, so valid data is available in the scratchpad as soon as power is applied to the device. read power supply [b4h] the master device issues this command followed by a read time slot to determine if any ds18b20s on the bus are using parasite power. during the read time slot, parasite powered ds18b20s will pull the bus low, and externally powered ds18b20s will let the b us remain high. see the powering the ds18b20 section for usage information for this command. table 3 . ds18b20 function command set command description protocol 1 - wire bus activity after command is iss ued notes temperature conversion commands convert t initiates temperature conversion. 44h ds18b20 transmits conversion status to master (not applicable for parasite - powered ds18b20s). 1 memory commands read scratchpad reads the entire scratchpad inclu ding the crc byte. beh ds18b20 transmits up to 9 data bytes to master. 2 write scratchpad writes data into scratchpad bytes 2, 3, and 4 (t h , t l , and configuration registers). 4eh master transmits 3 data bytes to ds18b20. 3 copy scratchpad copies t h , t l , and configuration register data from the scratchpad to eeprom. 48h none 1 recall e 2 recalls t h , t l , and configuration register data from eeprom to the scratchpad. b8h ds18b20 transmits recall status to master. read power supply signals ds18b20 power sup ply mode to the master. b4h ds18b20 transmits supply status to master. note 1: for parasite - powered ds18b20s, the master must enable a strong pullup on the 1 - wire bus during temperature conversions and copies from the scratchpad to eeprom. no othe r bus activity may take place during this time. note 2: the master can interrupt the transmission of data at any time by issuing a reset. note 3: all three bytes must be written before a reset is issued.
ds18b20 13 of 22 figure 11. r om commands flow chart cch ski p rom command master t x reset pulse ds18b20 t x presence pulse master t x rom command 33h read rom command 55h match rom command f0h search rom command ech alarm search command master t x bit 0 ds18b20 t x bit 0 ds18b20 t x bit 0 master t x b it 0 bit 0 match? master t x bit 1 bit 1 match? bit 63 match? master t x bit 63 n y y y y y n n n n n n n y y y ds18b20 t x bit 1 ds18b20 t x bit 1 master t x b it 1 ds18b20 t x bit 63 ds18b20 t x bit 63 master t x b it 63 bit 0 match? bit 1 match? bit 63 match? n n n y y y ds18b20 t x family code 1 byte ds18b20 t x serial number 6 bytes ds18b20 t x crc byte ds18b20 t x bit 0 ds18b20 t x bit 0 master t x b it 0 n y device(s) with alarm flag set? initialization sequence master t x function command (figure 12)
ds18b20 14 of 22 figure 12. ds18b20 function commands flow chart master t x function command y n 44h conver t temperature ? parasite power ? n y ds18b20 begins conversion device converting temperature ? n y master r x ?0s? master r x ?1s? master enables strong pullup on dq ds18b20 converts temperature master disables strong pullup y n 48h copy scratchpad ? parasite power ? n y master enables strong pull - up on dq data copied f rom scratchpad to eeprom master disables strong pullup master r x ?0s? copy in progress ? y master r x ?1s? n return to initialization sequence (figure 11) for next transac tion b4h read power supply ? y n parasite powered ? n master r x ?1s? master r x ?0s? y master t x t h byte to scratchpad y n 4eh w rite scratchpad ? master t x t l byte to scratchpad master t x config. byte to scratchpad y n y beh read scratchpad ? have 8 bytes been read ? n master t x reset ? master r x data byte from scratchpad n y master r x scratchpad crc byte master r x ?1s? y n b8h recall e 2 ? master begins data recall from e 2 prom device busy recalling data ? n y master r x ?0s?
ds18b20 15 of 22 1 - wire signaling the ds18b20 uses a strict 1- wire communication protocol to ensure data integrity. several signal types are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. the bus master initiates all these signals, with the exception of the presence pulse. initialization proc edure ? reset and presence pulses all communication with the ds18b20 begins with an initialization sequence that consists of a reset pulse from the master followed by a presence pulse from the ds18b20. this is illustrated in figure 13 . when the ds18b20 sends the presence pulse in response to the reset, it is indicating to the master that it is on the bus and ready to operate. during the initialization sequence the bus master transmits (t x ) the reset pulse by pulling the 1 - wire bus low for a minimum of 480 s. the bus master then releases the bus and goes into receive mode (r x ). when the bus is released, the 5k ? pullup resistor pulls the 1 - wire bus high. when the ds18b20 detects this rising edge, it waits 15 s to 60 s and th en transmits a presence pulse by pulling the 1 - wire bus low for 60 s to 240 s. figure 13. initialization timing read/write time slots the bus master writes data to the ds18b20 during write time slots and reads data from the ds18b20 during read time slots. one bit of data is transmitted over the 1- wire bus per time slot. write time slots there are two types of write time slots: ?write 1? time slots and ?write 0? time slots. the bus master uses a write 1 time slot to write a logic 1 to the ds18b20 and a write 0 time slot to write a logic 0 to the ds18b20. all write time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between individual write slots. both types of write time slots are initiated by the master pulling the 1- wire bus low (see figure 14). to generate a write 1 time slot , after pulling the 1 - wire bus low, the bus master must release the 1- wire bus within 15 s. when the bus is released, the 5k ? pullup resistor will pull the bus high. to generate a write 0 time slot, after pulling the 1- wire bus low, the bus master must con tinue to hold the bus low for the duration of the time slot (at least 60 s). line type legend bus master pulling low ds18b20 pulling low resistor pullup v pu gnd 1 - wire bus 480 s minimum 480 s minimum ds18b20 t x presence pulse 60- 240 s master t x reset pulse master r x ds18b20 waits 15 - 60 s
ds18b20 16 of 22 the ds18b20 samples the 1- wire bus during a window that lasts from 15 s to 60 s after the master initiates the write time slot. if the bus is high during the sampling window, a 1 is written to the ds18b20. if the line is low, a 0 is written to the ds18b20. figure 14. read/write time slot timing diagram read time slots the ds18b20 can only transmit data to th e master when the master issues read time slots. therefore, the master must generate read time slots immediately after issuing a read scratchpad [beh] or read power supply [ b4h ] command, so that the ds18b20 can provide the requested data. in addition, the master can generate read time slots after issuing convert t [44h] or recall e 2 [b8h] commands to find out the status of the operation as explained in the ds18b20 function command s section. all read time slots must be a minimum of 60 s in duration with a m inimum of a 1 s recovery time between slots. a read time slot is initiated by the master device pulling the 1 - wire bus low for a minimum of 1 s and then releasing the bus (see figure 14). after the master initiates the read time slot, the ds18b20 will begin transmitting a 1 or 0 on bus. the ds18b20 transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. when transmitting a 0, the ds18b20 will release the bus by the end of the time slot, and the bu s will be pulled back to its high idle state by the pullup resister. output 45 s 15 s v pu gnd 1 - wire bus 60 s < t x ?0? < 120 s 1 s < t rec < ds18b20 samples min typ max 15 s 30 s > 1 s master write ?0? slot master write ?1? slot v pu gnd 1 - wire bus 15 s master read ?0? slot master read ?1? slot master samples master samples start of slot start of slot > 1 s 1 s < t rec < 15 s 15 s 30 s 15 s ds18b20 samples min typ max line type legend bus master pulling low ds18b20 pulling low resistor pullup > 1 s
ds18b20 17 of 22 data from the ds18b20 is valid for 15 s after the falling edge that initiated the read time slot. therefore, the master must release the bus and then sample the bus state within 15 s from the start of the slot. figure 15 illustrates that the sum of t init , t rc , and t sample must be less than 15 s for a read time slot. figure 16 shows that system timing margin is maximized by keeping t init and t rc as short as possible and by locating the master sample time during read time slot s towards the end of the 15 s period. figure 15. detailed master read 1 timing figure 16. recommended master read 1 timing related application notes the f ollowing application n otes can be applied to the ds18b20 and are available on our website at www.maxim - ic.com . application note 27: understanding and using cyclic redundancy checks with maxim i button product s application note 122: using dallas' 1 - wire ics in 1 - cell li - ion battery packs with l ow - side n - channel safety fets master application note 126: 1 - wire communication through software application note 162: interfacing the ds18x20 /ds1822 1 - wire temperature sensor in a microcontroller environment app lication note 208: curve fittin g the error of a bandgap - based digital temperature sensor app lication note 2420: 1 - wire communication with a microchip picmicro microcontroller app lication note 3754: single - wire serial bus carries isolated power and data sample 1- wire subroutines that can be used in conjunction with a pplication n ote 74 : reading and writing i buttons via serial interfaces can be downloaded from the maxim website. v pu gnd 1 - wire bus 15 s vih of mast er t rc t int > 1 s master samples line type legend bus master pulling low resistor pullup v pu gnd 1 - wire bus 15 s vih of master t rc = small t int = small master samples
ds18b20 18 of 22 ds18b20 operation example 1 in this example there are multiple ds18b20s on the bus and they are using paras ite power. the bus master initiates a temperature conversion in a specific ds18b20 and then reads its scratchpad and recalculates the crc to verify the data. master mode data (lsb first) comments tx reset master issues reset pulse. rx presence ds18 b20s respond with presence pulse. tx 55h master issues match rom command. tx 64 - bit rom code master sends ds18b20 rom code. tx 44h master issues convert t command. tx dq line held high by strong pullup master applies strong pullup to dq for the duration of the conversion (t conv ). tx reset master issues reset pulse. rx presence ds18b20s respond with presence pulse. tx 55h master issues match rom command. tx 64 - bit rom code master sends ds18b20 rom code. tx beh master issues read sc ratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares the calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. ds18b20 operation example 2 in this example there is only one ds18b20 on the bus and it is using parasite power. the master writes to the t h , t l , and configuration registers in the ds18b20 scratchpad and then reads the scratchpad and recalculates the crc to verify the data. the master then copies the scratchpad contents to eeprom. master mode data (lsb first) comments tx reset master issues reset pulse. rx presence ds18b20 responds with presence pulse . tx cch master issues skip rom command. tx 4eh master issues write scratchpad command. tx 3 data bytes master sends three data bytes to scratchpad (t h , t l , and config). tx reset master issues reset pulse. rx presence ds18b20 responds with presence pu lse. tx cch master issues skip rom command. tx beh master issues read scratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares t he calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. tx reset master issues reset pulse. rx presence ds18b20 responds with presence pulse. tx cch master issues skip rom command. tx 4 8h master issues copy scratchpad command. tx dq line held high by strong pullup master applies strong pullup to dq for at least 10ms while copy operation is in progress.
ds18b20 19 of 22 absolute maximum ratings voltage range on any pin relative to ground .................................................................. - 0.5v to + 6.0v operating temperature range ....................................................................................... - 55 c to +125c storage temperature range ........................................................................................... - 55 c to +125c solder temperature ..................................................... refer to the ipc/jedec j - std - 020 specification. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics ( - 55c to +125c; v dd =3.0v to 5.5v) parameter symbol condition s min typ max units notes supply voltage v dd local power +3.0 +5.5 v 1 pullup supply voltage v pu parasite power +3.0 +5.5 v 1,2 local power +3.0 v dd thermometer error t err - 10c to +85c 0.5 c 3 - 55c to +125c 2 input logic - low v il - 0.3 +0.8 v 1,4,5 input logic - high v ih local power +2.2 the lower of 5.5 or v dd + 0.3 v 1, 6 parasite power +3.0 sink current i l v i/o = 0.4v 4.0 ma 1 standby current i dds 750 1000 na 7,8 active current i dd v dd = 5v 1 1.5 ma 9 d q input current i dq 5 a 10 drift 0.2 c 11 notes: 1) all voltages are referenced to ground. 2) the pullup supply voltage specification assumes that the pullup device is ideal, and therefore the high level of the pullup is equal to v pu . in order to meet the v ih spec of the ds18b20, the actual supply rail for the strong pullup transistor must include margin for the voltage drop across the transistor when it is turned on; thus: v pu_actual = v pu_ideal + v transistor . 3) see typical performance curve in figure 17. 4) logic - low voltages are specified at a sink current of 4ma. 5) to guarantee a presence pulse under low voltage parasite power conditions, v ilmax may have to be reduced to as low as 0.5v. 6) logic - hig h voltages are specified at a source current of 1ma. 7) standby current specified up to + 70 c. standby current typically is 3 a at + 125c. 8) to minimize i dds , dq should be within the following ranges: gnd dq gnd + 0.3v or v dd ? 0.3v dq v dd . 9) active curr ent refers to supply current during active temperature conversions or eeprom writes. 10) dq line is high (?hi gh - z? state) . 11) drift data is based on a 1000 - hour stress test at + 125 c with v dd = 5.5v.
ds18b20 20 of 22 ac electrical characteristics ? nv memory ( - 55c to +100c; v d d = 3.0v to 5.5v) parameter symbol condition s min typ max units nv write cycle time t wr 2 10 ms eeprom writes n eewr - 55c to +55c 50k writes eeprom data retention t eedr - 55c to +55c 10 years ac electrical characteristics ( - 55c to +125c ; v dd = 3.0v to 5.5v) parameter symbol condition s min typ max units notes temperature conversion time t conv 9 - bit resolution 93.75 ms 1 10 - bit resolution 187.5 11 - bit resolution 375 12 - bit resolution 750 time to str ong pullup on t spon start convert t command issued 10 s time slot t slot 60 120 s 1 recovery time t rec 1 s 1 write 0 low time t low0 60 120 s 1 write 1 low time t low1 1 15 s 1 read data valid t rdv 15 s 1 reset time high t rsth 480 s 1 reset time low t rstl 480 s 1,2 presence - detect high t pdhigh 15 60 s 1 presence - detect low t pdlow 60 240 s 1 capacitance c in/out 25 pf notes: 1) see the timing diagrams in figure 18. 2) under parasite power, if t rstl > 960 s, a power - on reset may occur. figure 17. typical performance curve ds18b20 typical error curve -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 50 60 70 temperature (c) thermometer error (c) mean error +3s error -3s error
ds18b20 21 of 22 figure 18. timing diagrams
ds18b20 22 of 22 maxim cannot assume responsibilit y for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at an y time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2008 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revisi on date description pages changed 030107 in the absolute maximum ratings section, r emoved the reflow oven temperature value of + 220 c. reference to jedec specification for reflow remains . 19 101207 in the operation ? alarm signaling section, a dded ?or equa l to? in the desciption for a th alarm condition 5 in the memory section, r emoved incorrect text describing memory. 7 in the configuration register section, r emoved incorrect text describing configuration register. 8 042208 in the ordering information table , added to - 92 straight - lead packages and include d a note tha t the to - 92 package in tape and reel can be ordered with either formed or straight leads. 2

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